This invention relates to a speech synthesizer and more particularly to a monolithic semiconductor device for providing a systematic control in synthesizing sound information.
The past and present-day investigations of synthesis of speech are significantly different in that the former is aimed at studying what is the best hardware to synthesize human voices and the latter is devoted toward the development of a new and unique program suitable to synthesis of speech, that is, a software for controlling the voice synthesizer.
In the past years, the synthesizing of speech was achieved mainly by a hardware architecture especially comprising a hard block including a storage memory for storing a number of sequences of synthesis and an instruction decoder (hereinafter referred to as "hard block A"), a hard block including a family of address registers, a family of counters for counting the number of data, the basic counts of voiced and voiceless sounds and registers for temporarily storing phonemic data and amplitude data (hereinafter referred to as "hard block B") and a hard structure including a multiplier for executing multiplications on the phonemic data and the amplitude data (hereinafter referred to as "hard block C"). Provided that the procedure of speech synthesis is implemented with such time-honored basic hard achitecture, the counters should comprise different sorts of logically wired flip flops with added increment and decrement functions, for example. A random logic structure including random connections of such logic elements as gates, flip flops and counters, however, has the difficulty that the area required for those elements is limited and the area required for wiring is enlarged and all of those elements are not easily implemented in an economical size. It is therefore not possible to put the speech synthesizer on a one-chip LSI semiconductor device. Furthermore, an increase in chip size causes an exponential increase in cost.
In an attempt to solve the above discussed problems, the inventors have discovered that the hard block A in the above synthesizer architecture may be replaced with a read only memory (ROM) and the hard block B having the functions of addressing, counting and temporarily storing the phonemic data be replaced with a read and write memory (RAM). In addition, they have recognized that the multiplier in the hard block C may be eliminated by loading the results of multiplications into part of a sound data memory ROM as a storing table. As a result, the inventors have achieved one-chip LSI implementation of the speech synthesizer. This success has the advantages of increasing the effective area of those elements, integration density and the number of the elements per unit area.
The speed of processing data for speech synthesis depends upon sampling frequency. In order to attain real-time processing, there is the troublesome problem of how to process sample data within a sampling interval. For example, the data should be processed with 125 usec and 62.5 usec when the sampling frequency is 8 KHz and 16 KHz, respectively. The length of the data which can be processed within 62.5 usec amounts to no more than 8 steps, making it difficult to execute a sequence or process within such 8 steps. The inventors sought a new method by which to increase processing speed even when the operating frequency (sampling frequency) is low. As a consequence, the inventors discovered that a new effective solution lies with determination of the word length of a ROM performing the functions of the hard block B. In other words, increasing the seeming processing speed can be achieved by choosing the word length of the ROM considerably longer than that of the data ROM (for example, the former is 18 bits long and the latter is 8 bits, 4K bytes). The word length of 18 bits makes it possible to execute abouts 500 steps of operation within. Assuming that the one-word length of the ROM is 18 bits, 5 bits are assigned to instruction bits, 5 bits are assigned to RAM address bits and the remaining 8 bits are assigned to operand and next address bits. With such an arrangement, it becomes possible to execute a number of operations at one time. Thus, it becomes possible to provide access to the RAM at high speed in response to the output of the control ROM. As a rule, in order to enhance the processing speed of an LSI chip, the ON resistances of the elements should be as low as possible and supply voltages should be as high as possible to accelerate charge migration. These requirements inevitably result in a substantial increase in chip size as well as a significant deterioration in yield.
The method of the present invention by which the one-word length of the the ROM is selected to be substantially longer than that of the data ROM may be named "horizontal instruction method", whereas the prior art ROM architecture (say, 8 bits) may be named "vertical instruction method."